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Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to the SPCR. Control bits SPE and MSTR may be restored by user software to their original state after the MODF bit has been cleared. It is also necessary to restore DDRD after a mode fault. Bits 3-0 — Not Implemented These bits always read zero. 3 Serial Peripheral Data l/O Register (SPDR) The serial peripheral data l/O register is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte, and this will only occur in the master device.

RCKB is zero and cannot be set while in normal operating modes. The diagram shown in Figure 5-7 and the data given in Table 5-3 and Table 5-4 illustrate the divider chain used to obtain the baud rate clock. Note that there is a fixed rate divide-by-16 between the receive clock (RT) and the transmit clock (Tx). The actual divider chain is controlled by the combined SCP[1:0] and SCR[2:0] bits in the baud rate register as illustrated. 907 K Baud 4800 Baud 4430 Baud *The clock in the “Clock Divided By” column is the internal processor clock MOTOROLA 5-12 SERIAL COMMUNICATIONS INTERFACE MC68HC11A8 TECHNICAL DATA NOTE The divided frequencies shown in Table 5-3 represent baud rates which are the highest transmit baud rate (Tx) that can be obtained by a specific crystal frequency and only using the prescaler division.

STRB pulses on writes to port B. Inputs latched into PORTCL on any active edge on STRA. Normal output port. Unaffected in handshake modes Driven as outputs if STRA at active level. Follows DDRC if STRA not at active level. Normal output port. Unaffected in handshake modes NOTE: 1. Set by active edge on STRA $1002 RESET 7 STAF 0 MOTOROLA 4-4 6 STAI 0 5 CWOM 0 4 HNDS 0 3 OIN 0 PARALLEL I/O 2 PLS U 1 EGA 1 0 INVB 1 PIOC MC68HC11A8 TECHNICAL DATA STAF — Strobe A Interrupt Status Flag This bit is set when a selected edge occurs on strobe A.

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68HC11 Technical Docs

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